RISC-v Asm

Course Overview An intensive exploration of advanced computer architecture and hardware-software co-design. The coursework focused on processor microarchitecture, memory hierarchy, cache coherence protocols (such as MSI), and hardware-level performance optimization. Assignments were heavily implemented in C and RISC-V Assembly to analyze instruction-level parallelism, pipeline behavior, and data-level parallelism via vector extensions. Core Laboratory Projects 1. Microarchitectural Profiling & Pipeline Hazards Co-designed and executed microbenchmarks in C to reverse-engineer hardware memory hierarchies and expose processor pipeline characteristics. ...

Course Overview An intensive exploration of the hardware-software interface, system-level programming, and modern computer microarchitecture. The coursework ranged from low-level memory management in C and implementing mathematical algorithms in pure RISC-V assembly, to building a pipelined RISC-V processor core from scratch at the digital logic level. Core Project: Game Logic and Low-Level Memory Management in C Developed a complete Snake game engine from scratch in C, focusing on dynamic memory allocation, pointer arithmetic, and the lifecycle management of complex data structures. ...